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integrated circuit systems, inc. general description features ICS9220 1227g?11/05/07 avdd2.5 1 28 vdd2.5 agnd 2 27 gnd irefy 3 26 gnd agnd 4 25 odclk_t0 clk_int 5 24 odclk_c0 clk_inc 6 23 gnd vdd2.5 7 22 vdd2.5 gnd 8 21 vdd2.5 smbclk 9 20 gnd smbdat 10 19 odclk_t1 oe 11 18 odclk_c1 as1 12 17 gnd as2 13 16 gnd bypass#/pll 14 15 vdd2.5 ICS9220 28-pin 4.4mm tssop block diagram programmable rambus tm xdr tm clock generator the ICS9220 clock generator provides programmable clock signals to support the rambus xdr tm memory subsystem and redwood logic interface. the ICS9220 has been optimized for 100mhz reference input that may or may not be modulated for spread spectrum. the ICS9220 provides 2 differential clock pairs in a space saving 28-pin tssop package and provides an off-the- shelf high-performance interface solution. figure 1 shows the major components of the ICS9220 xdr clock generator. these include the a pll, a bypass multiplexer and two differential output buffers. the outputs can be disabled by a logic low on the oe pin. an output is enabled by the combination of the oe pin being high, and 1 in its smbus output control register bit. the pll receives a reference clock, clk_int/c and outputs a clock signal at a frequency equal to the input frequency times a multiplier. table 2 shows the multipliers selectable via the smbus interface. this clock signal is then fed to the differential output buffers to drive the enabled clocks. disabled outputs are set to hi-z. the bypass mode routes the input clock, clk_int/c, directly to the differential output buffers, bypassing the pll. up to four ICS9220 devices can be cascaded on the same smbus. table 3 shows the smbus addressing and control for the four devices. 300 - 700 mhz clock source 2 open-drain differential output drives with short term jitter < 40ps spread spectrum compatible reference clock is differential or single-ended 100mhz smbus programmability for: - frequency multiplier - output enable - operating mode support systems where xdr subsystem is asynchronous to other system clocks 2.5v power supply xdr is a trademark of rambus pin configuration pll bypass mux rega regb clk_int clk_inc smbclk oe oe oe bypass#/pll smbdat as1 as2 odclk_c1 odclk_t1 odclk_c0 odclk_t0
2 ICS9220 1227g?11/05/07 pin descriptions pin # pin name pin type description 1 avdd2.5 pwr 2.5v analo g power pin for core pll 2 agnd pwr analog ground pin for core pll 3irefy out this pin establishes the reference current for the differential clock pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 4agnd pwranalo g ground pin for core pll 5 clk_int in "true" reference clock input. 6 clk_inc in "complementary" reference clock input. 7 vdd2.5 pwr power supply, nominal 2.5v 8 gnd pwr ground pin. 9 smbclk in clock pin of smbus circuitry, 5v tolerant 10 smbdat i/o data pin of smbus circuitry, 5v tolerant 11 oe in active high input for enabling outputs. 0 = tri-state outputs, 1= enable outputs 12 as1 in default smbus address select. 13 as2 in default smbus address select. 14 bypass#/pll in input to select bypass(fan-out) or pll (zdb) mode 0 = bypass mode, 1= pll mode 15 vdd2.5 pwr power supply, nominal 2.5v 16 gnd pwr ground pin. 17 gnd pwr ground pin. 18 odclk_c1 out "complementary" side of open drain differential clock output. this open drain output needs an external resistor network.. 19 odclk_t1 out "true" side of open drain differential clock output. this open drain output needs an external resistor network.. 20 gnd pwr ground pin. 21 vdd2.5 pwr power supply, nominal 2.5v 22 vdd2.5 pwr power supply, nominal 2.5v 23 gnd pwr ground pin. 24 odclk_c0 out "complementary" side of open drain differential clock output. this open drain output needs an external resistor network.. 25 odclk_t0 out "true" side of open drain differential clock output. this open drain output needs an external resistor network.. 26 gnd pwr ground pin. 27 gnd pwr ground pin. 28 vdd2.5 pwr power supply, nominal 2.5v
3 ICS9220 1227g?11/05/07 general smbus serial interface information for the ICS9220 how to write: ? controller (host) sends a start bit. controller (host) sends the write address per table 3 ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address per table 3 ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address per table 3 ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p byte n + x - 1 data byte count = x beginning byte n stop bit x byte index block write operation slave address table 3 beginning byte = n write start bit controller (host) t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address table 3 index block read operation slave address table 3 beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
4 ICS9220 1227g?11/05/07 smbus table: output enable control register pin # name control function type 0 1 pwd bit 7 test mode reserved for vendor rw disable enable 0 bit 6 reserved reserved rw - - 0 bit 5 reserved reserved rw - - 0 bit 4 reserved reserved rw - - 0 bit 3 reserved reserved rw - - 0 bit 2 reserved reserved rw - - 0 bit 1 odclk_t/c1 output control rw disable enable 1 bit 0 odclk_t/c0 output control rw disable enable 1 smbus table: address control register pin # name control function type 0 1 pwd bit 7 reserved reserved r - - 0 bit 6 as2 smbus address select r x bit 5 as1 smbus address select r x bit 4 reserved reserved r - - 0 bit 3 reserved reserved r - - 0 bit 2 reserved reserved r - - 0 bit 1 reserved reserved r - - 0 bit 0 reserved reserved r - - 0 smbus table: vendor & revision id register pin # name control function type 0 1 pwd bit 7 rid 3 r - - 0 bit 6 rid 2 r - - 0 bit 5 rid 1 r - - 0 bit 4 rid 0 r - - 0 bit 3 vid 3 r - - 0 bit 2 vid 2 r - - 0 bit 1 vid 1 r - - 0 bit 0 vid 0 r - - 1 see table 3 byte 0 - - - - - - - - byte 1 - - - - - - - - byte 2 - - - - - - - - revision id vendor id
5 ICS9220 1227g?11/05/07 smbus table: reserved register pin # name control function type 0 1 pwd bit 7 reserved reserved rw - - 0 bit 6 reserved reserved rw - - 0 bit 5 reserved reserved rw - - 0 bit 4 reserved reserved rw - - 0 bit 3 reserved reserved rw - - 0 bit 2 reserved reserved rw - - 0 bit 1 reserved reserved rw - - 0 bit 0 reserved reserved rw - - 0 smbus table: reserved register pin # name control function type 0 1 pwd bit 7 reserved reserved rw - - 0 bit 6 reserved reserved rw - - 0 bit 5 reserved reserved rw - - 0 bit 4 reserved reserved rw - - 0 bit 3 reserved reserved rw - - 0 bit 2 reserved reserved rw - - 0 bit 1 reserved reserved rw - - 0 bit 0 reserved reserved rw - - 0 smbus table: vco frequency control register pin # name control function type 0 1 pwd bit 7 post divider pll post divide rw divide by 2 divide by 4 1 bit 6 reserved reserved rw - - 0 bit 5 reserved reserved rw - - 0 bit 4 reserved reserved rw - - 0 bit 3 m div3 rw 0 bit 2 m div2 rw 0 bit 1 m div1 rw 1 bit 0 m div0 rw 0 - - byte 3 - - - - - - - - - - - byte 4 byte 5 - - - - - - - m divider programming b(3:0) the decimal representation of m and n divider in byte 5 and 6 will configure the pll vco frequency. vco frequency = 100 x {[ndiv(5:0)+2]/[mdiv(3:0)+2]} - - - -
6 ICS9220 1227g?11/05/07 smbus table: vco frequency control register pin # name control function type 0 1 pwd bit 7 reserved rw - - 0 bit 6 reserved rw - - 0 bit 5 n div5 rw 0 bit 4 n div4 rw 0 bit 3 n div3 rw 1 bit 2 n div2 rw 0 bit 1 n div1 rw 1 bit 0 n div0 rw 0 smbus table: byte count register pin # name control function type 0 1 pwd bit 7 0 bit 6 0 bit 5 0 bit 4 bc4 rw 0 bit 3 bc3 rw 0 bit 2 bc2 rw 1 bit 1 bc1 rw 1 bit 0 bc0 rw 1 byte count programming reserved reserved reserved writing to this register will c onfigure how many bytes will be read back, default is 07 = 7 bytes n divider programming b(5:0) the decimal representation of m and n divider in byte 5 and 6 will configure the pll vco frequency. vco frequency = 100 x {[ndiv(5:0)+2]/[mdiv(3:0)+2]} - b y te 7 - - - - - byte 6 - - - - - - -
7 ICS9220 1227g?11/05/07 pll multiplier table 2 shows the frequency multipliers in the pll, selectable by programming the mult0, mult1 and mult2 bits in the smbus multiplier control register. power up default is 4. table 2. pll multiplier programming selection 468 300.00000 4 1200.0000 6 18 84 10 1200.00 1800.00 2400.00 325.00000 4 1300.0000 4 13 82 0b 1300.00 1950.00 2600.00 350.00000 4 1400.0000 6 21 84 13 1400.00 2100.00 2800.00 366.66667 4 1466.6667 6 22 84 14 1466.67 2200.00 2933.33 375.00000 4 1500.0000 4 15 82 0d 1500.00 2250.00 3000.00 383.33333 4 1533.3333 6 23 84 15 1533.33 2300.00 3066.67 400.00000 4 1600.0000 6 24 84 16 1600.00 2400.00 3200.00 416.66667 4 1666.6667 6 25 84 17 1666.67 2500.00 3333.33 425.00000 2 850.0000 4 17 02 0f 1700.00 2550.00 3400.00 433.33333 2 866.6667 6 26 04 18 1733.33 2600.00 3466.67 450.00000 2 900.0000 6 27 04 19 1800.00 2700.00 3600.00 466.66667 2 933.3333 6 28 04 1a 1866.67 2800.00 3733.33 475.00000 2 950.0000 4 19 02 11 1900.00 2850.00 3800.00 483.33333 2 966.6667 6 29 04 1b 1933.33 2900.00 3866.67 500.00000 2 1000.0000 6 30 04 1c 2000.00 3000.00 4000.00 516.66667 2 1033.3333 6 31 04 1d 2066.67 3100.00 4133.33 533.33333 2 1066.6667 6 32 04 1e 2133.33 3200.00 4266.67 550.00000 2 1100.0000 6 33 04 1f 2200.00 3300.00 4400.00 566.66667 2 1133.3333 6 34 04 20 2266.67 3400.00 4533.33 583.33333 2 1166.6667 6 35 04 21 2333.33 3500.00 4666.67 600.00000 2 1200.0000 6 36 04 22 2400.00 3600.00 4800.00 616.66667 2 1233.3333 6 37 04 23 2466.67 3700.00 4933.33 633.33333 2 1266.6667 6 38 04 24 2533.33 3800.00 5066.67 650.00000 2 1300.0000 6 39 04 25 2600.00 3900.00 5200.00 666.66667 2 1333.3333 6 40 04 26 2666.67 4000.00 5333.33 note: byte 5 hex byte 6 hex asic multiplier all output values based on 100.000000mhz input clock postdiv b5b7 vco m b5b(3:0) n b6b(5:0) output
8 ICS9220 1227g?11/05/07 operating modes device id and smbus device address the device id (smb_a(2:1)) is part of the smbus device address. the least significant bit of the address designates a write or read operation. table 3 shows the addresses for four ICS9220 devices on the same smbus. table 4: operating modes byte 1 lxxxx z z hx 1xx hl0xx hh000 z z hh001 z clk_int/c hh010 clk_int/c z hh011 clk_int/c clk_int/c notes 1 bypass mode 2 power up default mode clk_int/c reserved for vendor test bit 7 bit 0 bit 1 odclk_t/c1 odclk_t/c0 byte 0 oe bypass#/ pll table 3. smbus device addresses device control function as2 as1 wr#/rd d8 0 d9 1 da 0 db 1 dc 0 dd 1 de 0 df 1 3 11011 0 1 0 1 0 0 1 hex address ics 9220 operation read write read write write read write read 0 1 2 8 bit smbus de vice addre ss including oper. 1
9 ICS9220 1227g?11/05/07 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . 0c to +85c storage temperature . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc characteristics - inputs ta = 0c to +85c; supply voltage avdd2.5, vdd2.5 = 2.5 v +/- 0.125v (unless otherwise stated) symbol conditions min typ max units v dd2. 5 , a vdd 2.375 2.625 v v i hclk 0.6 0.95 v v ilclk -0.15 0.15 v v ixclk 0.2 0.55 v v ixclk 0.15 v v th 0.35 0.5 vdd2. 5 v v ihse v th + 0.3 2.625 v v ilse -0.15 v th - 0.3 v v ih 1.4 2.625 v v il -0.15 0.8 v v ihsmb 1.4 3.465 2 v v ilsmb -0.15 0.8 v notes: 1 2 when using singled-ended clock input, v th is supplied to clk_intc as shown in figure 2. duty cycle of singled-ended clk_in is measured at v th . this range of smbus input high voltages allows the 9220 to co-exist with 3.3v, 2.5v and 1.8v devices on the same smbus. parameter supply voltage high-level input voltage low-level input voltage crossing point voltage difference in crossing point voltage input threshold voltage high-level input voltage for single-ended clk_in low-level input voltage - smbus clk_int, clk_inc singled-ended clk_in 1 oe, as1, as2, bypass#/pll smbclk, smbdat low-level input voltage for single-ended clk_in high-level input voltage low-level input voltage high-level input voltage - smbus
10 ICS9220 1227g?11/05/07 symbol condition min typ max units f = 300 to 636 mhz - 36 40 ps f = 635 to 800 mhz - 26 30 ps l 20 f offset = 20mhz, f out = 400mhz -128 ps dc 45 55 % t r , t f 20% to 80% of output voltage 140 300 ps t r-f 20% to 80% of output voltage - 100 ps z out 2 v ol = 0.9 v 1000 - ? notes: 1 2 duty cycle guaranteed by design and characterization, not 100% tested in production zout is defined at the output pins. dynamic output impedance output rise and fall times difference between output rise and fall time on same pin of a single device phase noise spectral purity ac characteristics-outputs parameter 1 t a = 0c to +85c; supply voltage avdd2.5, vdd2.5 = 2.5 v +/- 0.125v (unless otherwise stated) short term jitter (over 1 to 6 clock cycles) t j 2 dc characteristics - outputs ta = 0c to +85c; supply voltage avdd2.5, vdd2.5 = 2.5 v +/- 0.125v (unless otherwise stated) symbol conditions min typ max units t pu power within spec to outputs within spec 3ms t co smbus or mode select transition to outputs valid and within spec 3ms v ox measured as shown in fig. 3 0.9 1.1 v v cos measured as shown in fig. 3. excludes over and undershoot. 300 350 mv v ol, abs measured at odclk_t/c pins 0.85 v v iset v dd = 2.3v, v out = 1v 0.98 1.02 v i ol /i ref i ref is equal to v iset /r rc . tolerance of r rc <=+/-1%. 6.8 7 7.2 - i ol, abs measured at odclk_t/c pins with termination per figure 3. 45 - ma v olsmb i ol = 4 ma -0.4v i olsmb v ol = 0.8 v 6-ma i oz differential clock output pins - 50 ? notes: 1 low-level output voltage smbus low-level output current smbus tristate output current there is no output latenc y or g litches if a value written to an output re g ister is the same as its current contents. parameter power up latency state transition latency 1 differential output crossing voltage minimum current at v olabs output voltage swing (peak-to-peak singled ended) absolute output low voltage reference voltage for swing control current ratio of output low current to reference current at typical v dd2.5
11 ICS9220 1227g?11/05/07 thermal characteristics parameter symbol conditions min. typ. max. units ja still air 120 c/w ja 1 m/s air flow 95 c/w ja 3 m/s air flow 80 c/w thermal resistance junction to case jc 20 c/w thermal resistance junction to top of case jt still air 4.5 c/w maximum case temp 120 c thermal resistance junction to ambient symbol condition min typ max units t cyclei n 91011ns t c y c -t c y c 2 185 ps d tin over 10,000 cycles 40 60 % t r , t f 20% to 80% of input voltage 175 700 ps t r-f 20% to 80% of input voltage - 150 ps f inm 3 30 33 khz triangular modulation 0.6 % non-triangular modulation 0.54 % t sl(i) 20% to 80% of input voltage 1 4 v/ns c i nclk clk_int, clk_inc 7 pf c in vi = v dd2. 5 or gnd 10 pf t cycletst bypass mode 4 40 ns f smb 10 100 khz notes: 1 2 3 4 5 input clock slew rate input capacitance 5 clk_int/clk_inc rise and fall time difference between input rise and fall time on same pin of a single device spread spectrum modulation frequency input clock duty cycle cycle-to-cycle jitter ac characteristics-inputs t a = 0c to +85c; supply voltage avdd2.5, vdd2.5 = 2.5 v +/- 0.125v (unless otherwise stated) parameter clk_int/clk_inc cycle time 1 capacitance measured at f = 1 mhz, dc bias = 0.9v, vac <100mv. m i ndex 3 measured at (v ih(nom ) - v il(nom) )/2 and is the absolute value of the worst case deviation. measured at crossing points for differential clock input or at vth for single- ended clock input. if input modulation is used. input modulation is not necessary. the amount of allowed spreading for non-triangular modulation is determined by the induced downstream tracking skew. spread spectrum modulation index smbus clock frequency clk_int cycle time input capacitance 5
12 ICS9220 1227g?11/05/07 vth inpu t clock generator inpu t xdr xdr clock generator a. differential input b. single-ended input supply voltage clk_inc clk_int clk_int figure 1. differential and single-ended reference clock inputs clock output drivers figure 2 shows the clock driver equivalent circuit. the differential driver produces a specified voltage swing on the channel by switching the currents going into odclk_t and odclk_c. the external resistor r rc at the irefy pin sets the maximum current. the minimum current is zero. the voltage at the irefy pin, v irefy , is by design equal to 1 v nominally, and the driver current is seven times the current flowing through r rc . so, the output low current can be estimated as i ol = 7/ r rc . the driver output characteristics are defined together with the external resistors, r 1 , r 2 , and r 3 . the output clock signals are specified at the measurement points indicated in figure 2. table 5 shows example values for the resistors. r 1 , r 2 , and r 3 and the clock driver output impedance, z out , must match the impedance of the channel, z ch , to minimize secondary reflections. z out is specified as 1000 ohms, minimum to accomplish this. the effective impedance can be estimated by: (1000r 1 /(1000+r 1 )+r2) r 3 /(1000r 1 /(1000+r 1 )+r 2 +r 3 ) pull-up resistor r t terminates the transmission line at the load to minimize clock signal reflection signal reflections. table 5 shows the resistor values for establishing and effective source termination impedance of 49.2 ohms to match a 50 ohm channel. the termination voltages are 2.5 v for v ts and 1.2 v for v t . the resistor values r1 = 38.3 ohms, r 2 = 19.1 ohms, r 3 = 54.9 ohms and r rc = 200 ohms can be used to match a 28 ohm channel. table 5. example resistor values and termination voltages for a 50 ohm channel 1 symbol parameter value tolerance unit r 1 termination resistor 39.2 +/- 1% ? r 2 termination resistor 66.5 +/- 1% ? r 3 termination resistor 93.1 +/- 1% ? r t termination resistor 49.9 +/- 1% ? r rc swing control resistor 200 +/- 1% ? v ts source termination voltage 2.5 +/-5% v v t termination voltage 1.2 +/-5% v notes: 1 a different set of resistors is used in figure 2 when testing for maximum output current of the clock driver (i olabs ). these resistors are: r 1 = 23 ? , r 2 = 36.5 ? , r 3 = 52.3 ? , r t =28 ? , r rc = 118 ?
13 ICS9220 1227g?11/05/07 r 2 r 3 r t z ch r 1 measuremen t differential driver point r t z ch measurem ent point r 2 r 3 r 1 swing current contro l r rc v t v t v ts v ts iset odclk_t odclk_c figure 2. example system clock driver equivalent circuit t f 80% v(t) 20% t r v h v l figure 3. input and output voltage waveforms vx,n om vx+ vx- odclk_t odclk_c figure 4. crossing-point voltage input clock signal the ICS9220 receives either a differential or single-ended reference clock (clk_int/c). when the reference input clock is from a differential clock source, it must meet the voltage levels and timing requirements listed in the dc characteristics ? inputs and ac characteristics ? inputs tables. for a singled-ended clock input, an external voltage divider and a supply voltage, as shown in figure 2, provide a reference voltage v th at the clk_inc pin to determine the proper switching point for clk_int. the range of v th is specified in the dc characteristics ? inputs table.
14 ICS9220 1227g?11/05/07 t cycle,i t j = t cycle,i - t cycle, i+1 over 10,000 consecutive cycl es t cycle, i+1 odclk_t odclk_c figure 7. cycle-to-cycle duty cycle error figure 6. short-term jitter cycle (i) cycle (i+1 ) t pw+ (i) t cycle (i) t pw+ (i+1) t cycle (i+1) t dc,err = t pw+ (i) - t pw+ (i+1) and t pw- (i) - t pw- (i+1 ) t pw- (i) t pw- (i+1) odclk_t odclk_c figure 5. cycle-to-cycle jitter power sequencing supply voltages for the ICS9220 must be applied before, or at the same time and external input and output signals. t 4cycle, i t j = t 4cycle, i - t 4cycle, i+1 over 10,000 consecutive cyc les t 4cycle, i+ 1 odclk_t odclk_c
15 ICS9220 1227g?11/05/07 f nom (1-p m,in )*f nom 0.5/f m,in 1/f m,in t figure 8. input frequency modulation
16 ICS9220 1227g?11/05/07 ordering information ICS9220 y g lf-t index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c min max min max a--1.20--.047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 d e e1 4.30 4.50 .169 .177 e l 0.45 0.75 .018 .030 n a 0808 aaa -- 0.10 -- .004 variations min max min max 28 9.60 9.80 .378 .386 10-0035 4.40 mm. body, 0.65 mm. pitch tssop 6.40 basic 0.252 basic 0.0256 basic common dimensions in millimeters in inches common dimensions (173 mil) (25.6 mil) symbol see variations see variations 0.65 basic reference doc.: jedec publication 95, mo-153 n see variations see variations d mm. d (inch) example: designation for tape and reel packaging lead free, rohs compliant package type g = tssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y g lf- t
17 ICS9220 1227g?11/05/07 revision history rev. issue date description page # d 10/11/06 final release - e 04/06/07 updated ac output short term jitter specifications 10 f 04/09/07 updated ac output short term jitter specifications 10 g 11/05/07 updated to extended temperature range -

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